The currents in all terminals of an N-channel field effect transistor (NFET) can be severely degraded when a soft or hard dielectric breakdown event occurs from gate to drain. Gate-drain breakdown in NFETs is expected to become an increasingly prevalent failure mode as channel length is scaled, and is more problematic than a gate-pwell breakdown because an input/output node failure is more probable. The severity of post gate-drain dielectric breakdown may be due to the low resistance of the source-drain extension region, the large energy dissipated during breakdown between the gate and the strongly accumulated source-drain extension, and/or the microscopic details of the gate-to-drain breakdown path.
Time to first breakdown event has historically been applied as the time-to-breakdown used to assess the reliability of ultra thin gate dielectrics. However, some circuits can remain operative after first breakdown. Consequently, if the time to circuit failure can be extended beyond the first breakdown event, the corresponding relaxation in reliability requirements can enable higher safe operating voltages to achieve higher performance. It is therefore desirable to have the capability to simulate the effects of breakdown on circuit functionality. Such simulations are often performed using computer-based circuitry simulation systems, such as Simulation Program with Integrated Circuit Emphasis (SPICE) and suitable device models. Effective simulation of post-breakdown circuit operation requires an equivalent circuit that accurately models the post breakdown electrical characteristics of the transistor.